Integrated circuits and other electronic systems often include signal lines that carry digital signals that transition between logic high voltage levels and logic low voltage levels. Undesirable capacitive coupling can develop between such digital signal lines if they are in close proximity to each other within the integrated circuit or electronic system.
FIG. 1 (prior art) is an embodiment 100 of a block diagram for digital signal lines, for example, within an integrated circuit. Embodiment 100 represents a cross-section of an integrated circuit with the surface of the integrated circuit being parallel with signal lines 102 and 104. Signal lines 102 and 104 represent digital signal lines that flow in one direction across the integrated circuit. Elements 106, 108, 110, 112, and 114 represent digital signal lines that are running perpendicular to signal lines 102 and 104 within the integrated circuit. During operation, capacitive coupling can occur between these digital signal lines, particularly, if they are changing voltage levels in close proximity to each other. For example, this can occur when one signal line is carrying a clock signal and another signal line is carrying a data output signal. The capacitor symbols shown between adjacent digital signal lines 102, 104, 106, 108, 110, 112, and 114 in embodiment 100 represent parasitic capacitances that can be created by this capacitive coupling between digital signal lines. This parasitic capacitance is often undesirable and can reduce the performance of digital signaling within an integrated circuit and/or electronic system that includes the digital signal lines.
Return-to-zero signaling, as described below with respect to FIG. 2 (Prior Art) and FIG. 3 (Prior Art), has been used to reduce capacitive coupling by keeping voltage levels for clock or a first data signals from moving in one direction while voltage levels for an adjacent second data signals move in an opposite direction.
FIG. 2 (prior art) is a block diagram of an embodiment 200 for return-to-zero signaling circuitry that can be used to reduce capacitive coupling. As depicted, a data register 204 receives input data 201 and a clock signal (CLK) 202. The data register 204 then outputs data 206 based upon a clock edge for the clock signal (CLK) 202, such as a rising clock edge. Return-to-zero circuitry 208 receives the data 206 and the clock signal (CLK) 202, and the return-to-zero circuitry 208 outputs return-to-zero (RTZ) data 210. In particular, if data 206 is at a low logic level for a clock cycle, the return-to-zero circuitry 208 outputs a low logic level for the RTZ data 210 throughout the full clock cycle. However, if the data 206 is at a high logic level for a clock cycle, the return-to-zero circuitry 208 outputs a high logic level for the RTZ data 210 during a first portion of the clock cycle but then returns the RTZ data 210 to a low logic level during a second portion of the clock cycle before the end of the clock cycle.
FIG. 3 (prior art) is an embodiment 300 of a timing diagram for return-to-zero signaling. The y-axis represents logic levels for the clock signal (CLK) 202, data 206, and RTZ data 210. The x-axis represents time. Ten clock cycles are indicated from clock cycle T0 to clock cycle T9. Clock cycle T10 is started, but the complete cycle is not shown. The logic levels for the data 206 for these ten clock cycles (T0-T1-T2-T3-T4-T5-T6-T7-T8-T9) are 0-1-1-0-1-0-1-1-1-0, respectively. High logic levels are indicated as a logic “1,” and low logic levels are indicated as a logic “0.” While the logic levels for data 206 are indicated for each clock cycle, the logic levels for the RTZ data 210 are indicated for each half-cycle. For the embodiment 300, the clock cycle begins at each rising edge of the clock signal (CLK) 202, and the return-to-zero is configured to occur on the falling edge for the clock signal (CLK) 202. Thus, each time the logic level for the data 206 is a high logic level, the RTZ data 210 will return to zero (e.g., low logic level) for the last half-cycle on the falling edge of the clock signal (CLK) 202, as indicated by arrows 302, 304, 306, 308, 310, and 312. Thus, the logic levels for the RTZ data 210 for each half-cycle of the ten clock cycles (T0-T1-T2-T3-T4-T5-T6-T7-T8-T9) are 00-10-10-00-10-00-10-10-10-00, respectively. As depicted, the logic level for the RTZ data 210 stays low for both half-cycles when the data 206 is at a low logic level (e.g., cycles T0, T3, T5, T9). The logic level for the RTZ data 210 is high for the first half-cycle and returns to zero for the second half-cycle when the data 206 is at a high logic level (e.g., cycles T1, T2, T4, T6, T7, T8).
As indicated above, the return-to-zero signaling reduces capacitive coupling between clock and data signal lines by keeping the clock signal from moving in one direction while an adjacent data signal is moving in an opposite direction. In particular, because the RTZ data 210 has always transitioned to a low logic level by the next clock cycle, the clock signal (CLK) 202 and the RTZ data 210 are kept from moving in opposite directions at the same time.